Intel has announced a new high-performance APU: three five-fold upgrades to hit 10 trillion times

2022-06-24 0 By

In addition to the 13-16 generation Core processors and new technology, Xeon Xeon processors, Arc flash graphics, And Arctic Sound-M multimedia card, Intel announced today a special Falcon Shores.It is based on x86 Xeon processor platform (compatible with socket interface), and integrates Xe HPC GPU for high performance computing, flexibly equipped with the number of core, combined with the next generation of packaging, memory, IO technology, to form a powerful “APU”.According to Intel, this flexible architecture can meet all supercomputing load requirements, bringing huge performance gains, efficiency gains, and simplifying GPU programming for large intensive computing, AI training models.Specifically, compared to today’s levels, the power ratio can be increased by a factor of five, x86 computing density can be increased by a factor of five, and memory capacity and density can be increased by a factor of five.Falcon Shores products will ship in 2024.It is part of Intel’s HPC-AI supercomputing strategy and is one of the major steps towards achieving a ZettaFLOS(ten trillion trillion) supercomputer by 2027, which will require a thousand-fold increase in computing performance over the next five years over the current exascale of calculations.In a similar vein, AMD is also reportedly planning to integrate its HPC Instinct GPU into zen4-based Skylon processors.Separately, Intel announced that the Ponte Vecchio, a high-performance computing GPU for exascale calculations, will ship as planned later this year, first to the U.S. Department of Energy’s Aurora supercomputer.Intel claims that the Ponte Vecchio met industry-leading performance standards in the face of complex financial services workloads and demonstrated 2.6 times better performance than market-leading solutions.The Ponte Vecchio will be the first product of Intel’S Xe HPC high-performance computing architecture, integrating more than 100 billion transistors, using five different processes and integrating up to 47 tiles internally.These include computing units, Rambo cache units, Foveros packaging units, base units, HBM units, Xe link units, EMIB units, and so on.